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Data Slicing Techniques for UH
2006年05月07日 13:28
不详 作者：不详
关键字：
Amplitude-shift keying (ASK) and on-off keying (OOK) receivers are used for intermittent low-data-rate a licatio like RKE, home security, garage-door openers, and remote controls. The data that comes to an ASK or OOK receiver from a remote tra mitter is reco tructed in the data slicer. The data slicer is, therefore, an integral part of ASK and FSK receivers that operate in the 260MHz to 470MHz short-range UHF band under the rules of FCC Part 15.231. This a lication note explai the operation of the data slicers found in Maxim's UHF receivers, including the MAX1470, MAX1473, and MAX1471, and tra ceivers like the MAX7030 and MAX7032.
Introduction
In its simplest form, the data slicer is an analog comparator that compares the demodulated ASK signal with a threshold. If the demodulated signal voltage exceeds the threshold, the comparator output goes high, usually to the su ly voltage. If the demodulated signal goes below the threshold, the comparator output goes low, usually zero volts or ground.
This a lication note reviews two a ects of data slicing: forming the comparator threshold, and preventing the comparator output from 'chattering' when no signal is present. The latter operation, often called 'squelching', can be done by introducing simple voltage offsets onto either pin of the data comparator. This offset can come directly from the power su ly or from using hysteresis, which is the proce of feeding back part of the output voltage from the data slicer comparator.
We will show three different ways to form the threshold, and three different ways to introduce squelch, all of which can be done by adding a few external resistors and/or capacitors.
Demodulated ASK Signal
The Maxim ASK receivers use a demodulator that is a carefully designed limiting IF amplifier. This amplifier produces a voltage that is proportional to the logarithm of the i ut IF signal power. When no signal is present, the voltage formed by the amplifier co ists of a quiescent DC value with a small time-varying noise voltage riding on it.
Figure 1
shows the waveform for the demodulator output in re o e to an ASK-modulated signal. The waveform will go back and forth between the quiescent voltage, V
, when the signal is keyed off, and the signal voltage, V
, when the signal is keyed on. In the
is typically about 1.2V and V
ranges from about 40mV at se itivity to about 1V at very high signal levels.
Figure 1. ASK demodulator output.
Data Slicer Block Diagrams
Figure 2
shows a block diagram of the MAX1473 ASK receiver. This a lication note focuses on the three operational amplifiers and the seven pi at the bottom right of the diagram that comprise the data slicer. The same functional blocks are redrawn in
Figure 3
to illustrate the function of each circuit more clearly. The reference designators for the resistors and capacitors in these figures are the same as those in the
schematic. The operational amplifier, U1, and its components form the Sallen-Key data filter, which smoothes the output of the detected amplitude from the ASK demodulator. The operational amplifier, U2, and its components form the data slicer comparator, while the peak-detecting operational amplifier, U3, and its components form the peak-detector output. We can now focus on individual parts of this circuit to understand the various optio within the data-slicing operation.
Figure 2. Block diagram of the MAX1473 ASK receiver.
Figure 3. Block diagram of the data-slicer blocks in the MAX1473, including external components.
The Fundamental Data-Slicing Circuit
Figure 4
shows the simplest data-slicing circuit. The output of the data filter, DFO, goes to the positive pin of the data slicer comparator, DSP, and also forms the slicing threshold voltage at DSN by pa ing through a simple RC lowpa filter. When the detected and filtered ASK signal, DFO, pa es through the lowpa filter formed by R1 and C4 and settles, the DC value of the DSN pin is halfway between the maximum and minimum voltage of that signal.
Figure 5
illustrates the waveforms at DSP and DSN, using the voltages V
from Figure 1. Notice that the steady-state voltage at DSN is V
/2. This circuit functio well when the received data stream has enough extra bits at the begi ing of a packet or frame (in the form of a preamble or synch pattern) that it can afford to lose while the R1-C4 circuit charges up to the correct slicing threshold. When the first bits of a sequence need to be detected, the circuit that forms the threshold voltageat DSN needs to reach that voltage quickly. This is where the peak detector can help.
Figure 4. Fundamental data-slicing circuit.
Figure 5. DSN and DSP signal for fundamental data-slicing threshold formation.
Data Slicer with Rapid Threshold Formation
Adding a voltage from the peak detector in the ASK receivers can accelerate the formation of the data-slicing threshold DSN. The circuit in
Figure 6
illustrates how the contributio to DSN from the data filter and the peak detector combine to produce a rapidly re onding threshold voltage. By co idering DFO and PDOUT as two independent voltage sources, we can use the Superposition technique (find the re o e from each source alone, then add the re o es) to determine the voltage at DSN. The contribution from the peak detector is an i tantaneous voltage jump through the capacitive divider formed by C13 and C4. This voltage jump decays to a steady-state value determined by the resistive divider formed by R1 and R2. The contribution from the R1-C4 lowpa filter is the same slowly rising threshold from the fundamental data-slicer circuit. By choosing the two R and two C values carefully, the two contributio can complement one another and form a threshold voltage at DSN that ideally jum immediately to the correct threshold and stays there.
Figure 6. Circuit and waveforms for rapid threshold formation.
Figure 7
illustrates two DSN waveforms for two different sets of resistors and capacitors. The combination of components that produces a threshold voltage at DSN closest to an i tantaneous jump obeys the guideline below:
Figure 7. Combined DSN voltage vs. time using a peak detector.
We can illustrate the choice of the R's and C's with a ecific example. For an ASK data rate of 4k NRZ, the R1-C4 lowpa filter should have a time co tant of about 5-bit intervals, which is 5 x 0.25ms, or 1.25ms. A good choice of R1 and C4 is:
R1 = 25 k
and C4 = 0.047 F
We choose C13 equal to C4, and make R2 much larger than R1 (a factor of 10 is good):
R2 = 250 k
and C13 = 0.047 F
This choice will cause the threshold voltage DSN to jump from V
/2, then settle to V
+ 0.55V
Notice that this a roach to establishing a rapid slicing threshold creates a small error in the threshold. Moreover, the time co tant a ociated with the threshold voltage's change from its initial to final value, which is a very small change, is given by the product below:
Time Co tant = (R1 || R2 x (C4 + C13))
This is a roximately twice the time co tant of the R1-C4 smoothing circuit. We could correct for this change by reducing each capacitor value, but that is not nece ary. Because the threshold changes very little after its initial jump, the time co tant is not as critical as it is in a circuit that lacks the peak-detector contribution.
Data Slicer with Dual Peak Detectors
There is a minor drawback to using the single peak detector in combination with the R-C smoothing circuit to form the slicing threshold: the final threshold value differs slightly from its ideal value which is halfway between the maximum and minimum voltage that comes from the data filter.
Using a maximum and minimum peak detector is one way to improve the rapid establishment of the slicing threshold. The
ASK/FSK receiver, the
FSK receiver, and the
tra ceivers have maximum and minimum peak detectors so that the single R-C smoothing circuit is not needed.
Figure 8
shows these peak detectors, each with an external resistor and capacitor. Each capacitor holds the peak voltage, and each resistor provides a discharge path for the a ociated capacitor. This design allows the peak detectors to dynamically follow any peak changes in the data-filter output voltages. The maximum and minimum peak detectors can be used together to form a data-slicer threshold voltage at a value midway between the maximum and minimum voltage levels of the data stream. The RC time co tant of these R-C pairs should be set to about five times the bit interval, as it is in the simple threshold smoothing circuit described earlier in this a lication note.
Figure 8. Data-slicer circuit with maximum and minimum peak detectors.
If something causes a significant change in the magnitude of the baseband signal, such as an AGC gain switch or a power-up tra ient, the peak detectors may 'catch' a false level. If a false peak is detected, the slicing level is incorrect. Because the RC time co tants are several bits long, the peak detectors may not recover rapidly. The Maxim receivers with dual peak detectors, however, all have at least one provision for resetting the peak detector outputs: the receivers momentarily allow the peak detectors to track the signal. In the MAX7042 FSK receiver, the peak detectors are reset by momentarily pulling the ENABLE pin low, then returning it to a logical high setting. The MAX7030 and MAX7031 tra ceivers reset the peak detectors the same way, but also reset the peak detectors whenever the AGC function changes state or the T/R switch enters the receive state. The MAX1471 ASK/FSK receiver and the MAX7032 ASK/FSK tra ceiver reset the peak detectors through their serial ports, and also automatically reset the peak detectors whenever the receiver emerges from the sleep mode.
Adding Basic Squelch to the Data Slicer
In the a ence of an ASK signal, the ASK detector output co ists of a DC voltage with a time-varying noise voltage whose peak-to-peak value is about 20mV. This noise voltage a ears as the data-slicer comparator swings back and forth acro the DSN threshold voltage, causing the comparator's output to 'chatter', that is, to jump rapidly and randomly back and forth between the su ly voltage and ground. This behavior often wakes up microproce ors u ece arily and can sometimes add noise to the power-su ly lines. One way to stop this chatter is to use a simple squelch circuit, which adds a small DC offset to either the positive (DSP) or negative (DSN) pin of the data slicer.
Figure 9
shows simple squelch circuits that use the power su ly as the source of the DC offset. Usually, all you need is a large resistor that is 50 to 100 times the value of the resistor between the data-filter output DFO and either i ut pin on the comparator. In the first circuit of Figure 9, the small offset is added to DSP. If the offset is about 30mV, then two things will ha en. Firstly, the noise riding on the DC voltage at DSP in the a ence of a signal will never take the DSP voltage below the level of the threshold at DSN; and, secondly, the DATAOUT pin will be held high, i.e., V
. In the second circuit of Figure 9, the offset is added to DSN. Now the noise that rides on the DC voltage at DSP will never take the DSP voltage above the increased threshold at DSN and the DATAOUT pin will be held low, i.e., GND. The squelch circuit reduces se itivity slightly (about 1dB to 2dB when the resistive divider is chosen carefully), and causes a slightly wider positive data pulse and slightly narrower negative data pulse at DATAOUT when a demodulated signal is present.
Figure 9. Two simple squelch circuits using a su ly voltage.
Squelch from Dual Peak Detectors
Another simple squelch circuit can be formed by using the dual peak detectors in Figure 8 above. Making the two resistors slightly unequal will shift the threshold above or below the midpoint of the two peak voltages, depending on which resistor is larger. If the threshold is set slightly above the midpoint by 30mV to 50mV, the DATAOUT pin will stay low when no signal is present. Similarly, if the threshold is set slightly below the midpoint, the DATAOUT pin will stay high when no signal is present.
Adding Resistive Hysteresis to the Data Slicer
You can also use a large resistor to tie the DATAOUT pin from the data slicer to the DSP pin .
Figure 10
shows the equivalent circuit for resistive hysteresis. This a roach has almost the same effect as co ecting V
to the DSP pin through a resistor. The only difference here is that, when a demodulated signal is present, the small offset at DSP is there only during the positive swing of the demodulated data. Hence, the increase in the width of the positive data pulse at DATAOUT is slightly le , because the leading edge of the positive data pulse is not advanced by the presence of an offset.
Figure 10. Resistive hysteresis circuit for squelch function.
Adding Capacitive Hysteresis to the Data Slicer
Capacitive hysteresis offers a compromise between exce ive chattering of the DATAOUT signal and the reduced se itivity that comes from a squelch or resistive hysteresis. The circuit for capacitive hysteresis is shown in
Figure 11
Just as in resistive hysteresis, a small fraction of the DATAOUT signal is fed back to the DSP pin, this time through the capacitive divider C7-C9. Typical capacitor values are 10pf for C7 and 1000pf for C9. The offset added to DSP differs because it is a tra ient offset that decays with a time co tant given by:
R8 x (C9 + C7)
Depending on the length of the time co tant, the offset kee the noise on DSP from going below the slicing threshold until the offset decays. This effectively increases the time that the DATAOUT pin stays high, thereby reducing the frequency of the DATAOUT chatter. While capacitive hysteresis does not eliminate chatter altogether, it reduces the number of tra itio .
Notice that the presence of C9 creates another lowpa filter with R8 in the demodulated ASK signal path. The pole a ociated with this filter time co tant should be larger than the bandwidth of the Sallen-Key data filter, so that it does not make the filtered signal too sluggish.
Figure 11. Capacitive hysteresis circuit and waveforms.
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Copyright 2006-2011
elecfa .com
.All Rights Reserved 粤ICP备07065979号Data slicing system
United States Patent 5301023
A tract:
A slice circuit for a data signal includes a clamp for clamping the data signal and a comparator having a first i ut coupled to the clamp, a second i ut coupled to a filter and an output coupled to a D/A converter. The output of the D/A converter is coupled to the filter such that a pulse width modulated signal is developed in the comparator output which is converted to a DC voltage by the D/A converter and filter for controlling the data slice level. The pulse width modulated signal is the sliced data.
Inventors:
Zato, Thomas J. (Palatine, IL)
A lication Number:
08/045275
Publication Date:
04/05/1994
Filing Date:
04/07/1993
Export Citation:
A ignee:
Zenith Electronics Corp. (Glenview, IL)
Primary Cla :
Other Cla es:
348/473,
348/E7.022
International Cla es:
H04N7/035
H04N7/035
; (IPC1-7): H04N7/087; H04N7/08
Field of Search:
358/147, 358/146, 358/142, 358/13, 375/76, 375/22
View Patent Images: US Patent References:
5223930
June, 1993
358/147
5136382
August, 1992
358/147
4873702
October, 1989
4667235
May, 1987
Nozoe et al.
358/147
4620227
October, 1986
Levin et al.
358/147
4602374
July, 1986
Nakamura et al.
4561100
December, 1985
Asao et al.
Foreign References:
JP62084687
April, 1982
JP62084686
April, 1987
Primary Examiner:
Groody, James J.
A istant Examiner:
Metjahic, Safet
Parent Case Data:
This a lication is a continuation of
a lication Ser. No. 780,698 filed Oct. 18, 1991.
Claims:
What is claimed is:
1. A method of slicing a data signal comprising:
clamping the data signal to a reference level;
a lying the clamped data signal to one i ut of a comparator to produce a sliced output;
sampling the sliced output of the comparator with a high frequency dot clock to produce a series of positive and negative logic level a lying the series of positive and negative logic levels to a D/A converter;
filtering the output of the D/A converter to develop a DC voltage; and
a lying the DC voltage to the other i ut of said comparator to adjust the slice level of the comparator.
2. The method of claim 1 wherein said data signal is included in a television signal line and is preceded by a horizontal sync pulse, the tip of said horizontal sync pulse establishing said reference level.
3. A data slice circuit comprising:
clamp mea for clamping a received data signal to a reference level;
a comparator having a first i ut coupled to said clamp mea , a second i ut and an output;
mea for sampling the output of said comparator with a high frequency dot clock to develop a series of positive and negative logic levels for a period of said data signal;
a D/A converter coupled to said comparator output and receiving said series of positive and negative logic level and
filter mea coupled between the output of said D/A converter and said second i ut of said comparator for developing a DC voltage representative of said series of positive and negative logic levels and for a lying said DC voltage to said second comparator i ut for adjusting the slice level of said comparator.
4. A method of optimizing the slice level of a digital data signal comprising a run-in portion and a data portion of the same data rate comprising:
clamping the digital data signal to a reference level;
a lying the clamped data signal to one i ut of a comparator for slicing the clamped data signal at a first level;
sampling the sliced data signal with a high frequency dot clock to generate a series of positive and negative logic levels for a period of the sliced data signal;
a lying said series of positive and negative logic levels to a D/A converter;
filtering the output of said D/A converter to develop a DC voltage based upon said series of positive and negative logic level and
a lying the Dc voltage to another i ut of said comparator to adjust said first level.
Description:
CROSS REFERENCE TO RELATED APPLICATIONS
This invention is related to the inventio described and claimed in a lication Ser. No. 07/781,059, entitled DATA SAMPLING SYSTEM and a lication Ser. No. 07/779,442, entitled CLOSED CAPTIONED DATA LINE DETECTION SYSTEM, both in the name of T. Zato and both a igned to Zenith Electronics Corporation.
BACKGROUND OF THE INVENTION AND PRIOR ART
This invention relates generally to on screen di lay systems for television receivers and ecifically to on screen di lay systems for developing subtitles on the television receiver viewing screen for the benefit of the hearing impaired. More particularly, this invention is concerned with a method of slicing data prior to sampling thereof.
Modern television receivers often incorporate on screen di lays, usually for di laying the time, date and cha el number. Such di lays are also used for controlling various functio such as volume, color, tint, etc. and for so-called picture-in-picture di lays. The size and location of the di layed information is often viewer-controllable by mea of a remote control device and the microproce or in the television receiver. Many television receivers also include "teletext" through which a wide range of print and graphics information may be presented to a viewer. Teletext information is received from coded data that is tra mitted in the vertical blanking interval (VBI) of the television signal, ecifically on one or more designated horizontal lines in the VBI.
Recently, in an effort to better serve viewers who are hearing impaired, the FCC has mandated that certain cla es of television receivers must be capable of di laying explanatory subtitles with the video picture. The subtitles will enable a hearing impaired viewer to follow the se e of the dialogue accompanying the televised program and will be available when the receiver is placed in a caption mode by operation of a caption di lay control. In the normal television viewing mode, the caption feature will not be activated and subtitles will not a ear on the television screen.
The captioned data will be encoded on line 21 of the odd field of the television signal and must have ecific characteristics. The information on line 21 will co ist of a run-in signal, comprising seven cycles of a 0.503 megahertz clock signal immediately following the end of the horizontal sync signal blanking level. The run-in signal is followed by a start sequence co isting of two 0 bits and a 1 bit, which is referred to as the start bit. The start bit is in turn followed by two bytes of either control information or data. The run-in signal commences at 10.074 microseconds from the leading edge of the line 21 horizontal sync pulse, the start bit commences at 27.452 microseconds from the start of horizontal sync and the following two bytes of data (or control information) occupy another 33.764 microseconds. The captioned data only a ears on line 21 and is not present in the corre onding line in the even field. Co equently, the system for recovering the captioned data must be able to find line 21 to recover that data.
Conventional line detection circuits are well known in the art for detecting data on selected lines in the television signal VBI. The format of NTSC television signals is such that the line numbers commence after the vertical sync pulse. In a receiver where the horizontal and vertical synchronizing signals are developed by countdown circuits, any particular line number may be readily found. In analog receivers and in VCRs, the nature of vertical sync recovery circuits precludes the use of a simple horizontal pulse counting arrangement to locate a given horizontal line. With such analog recovery circuits, it is not uncommon to reach line 21 by counting 16 or 17 horizontal pulses after the recovered vertical sync pulse. Further, in VCRs, artificial vertical blanking intervals are generated during ecial effects such as pause and slow motion and one ca ot simply count horizontal sync pulses (after recovery of the vertical sync pulse) to determine a particular line in the VBI.
As mentioned, where the horizontal and vertical timing signals are derived by countdown circuits from a common clock, the problem of identifying horizontal line 21 is relatively simple. However, clock countdown circuits are not used in the majority of analog television receivers and the need to quickly and economically bring closed captioning to the marketplace has presented television manufacturers with a major o tacle. Thus there is a need in the art for a low cost closed caption detection system that 1) can reliably find the VBI line that carries the closed captioned data, 2) adjusts the "slice" level of the data for reliable detection, and 3) samples the data reliably without elaborate synchronizing systems.
OBJECTS OF THE INVENTION
A principal object of the invention is to provide a novel closed caption detection system.
Another object of the invention is to provide a closed caption detection system that may be used in a wide range of television receivers.
A further object of the invention is to provide a closed caption detection system for television receivers that is economical, simple and reliable.
A feature of this invention is a method of slicing data prior to sampling thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects and advantages of the invention will be a arent upon reading the following description in conjunction with the drawings, in which:
FIG. 1 is a simplified block diagram of a closed caption detection system co tructed in accordance with the inventio FIG. 2 is a representation of line 21 showing the closed caption run-in signal and informatio FIG. 2A denotes the window for the run-in signal in alignment with the first portion of line 21 of FIG. 2;
FIGS. 3A-3E are graphical illustratio of optimized data slicing in accordance with one a ect of the inventio and
FIG. 4 is a simplified flow chart of portio of the operation of the closed captioned data system of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, a source of video i ut signal (not shown) is a lied to a synchronizing signal clamp 10 where the video signal is clamped at the level of the horizontal sync pulse. The output of clamp 10 is su lied to one i ut of a data slicer 12 and to a line 21 find circuit 14. Data slicer 12 comprises a comparator, the other i ut of which is a DC potential su lied by a filter 16, which may be a simple resistance-capacitance network. Slicer 12 in turn su lies a logic circuit 18 which operates a digital to analog (D/A) converter 20, the output of which is a lied to the i ut of filter 16. Slicer 12 also su lies sliced data to a sample circuit 22 which is controlled by logic circuit 18. Sources (not illustrated) of horizontal (H) and vertical (V) sync a ly suitable signals to the line 21 find circuit 14 which su lies an enable signal for logic circuit 18. A relatively high frequency dot clock signal (a roximately 8 MHz) is coupled to line 21 find circuit 14 and to logic circuit 18 for sampling purposes. An auto/manual control signal to logic circuit 18 overrides the automatic slicing circuit and enables direct software control of the slicing level. This will be described below.
Operation of the system is under general software control using the core microproce or in the television receiver (neither of which is shown). The received television signal is proce ed in accordance with standard techniques and the video signal is a lied to sync tip clamp 10 where the signal is clamped or referenced to horizontal sync tip level. A software routine is run to find line 21 based upon the nature of the captioned data, as will be described below, and in accordance with the invention claimed in copending a lication Ser. No. 07/779,442, above. In accordance with the present invention, the data is sliced to produce logic level voltage pulses and the slicing level is automatically adjusted to produce a 50% pulse duty cycle, subject to a manual override in the event a different duty cycle is desired. The logic circuit, again under software control, determines the a ropriate sampling rate for recovering the encoded data, and the recovered data is su lied to the system for further proce ing. The latter invention is claimed in copending a lication Ser. No. 07/781,059, above. While not shown, it is a umed that the receiver includes an alpha-numeric character generator and suitable control circuitry for developing a ropriate subtitle di lays in re o e to the encoded data i ut.
In FIG. 2, the format of line 21 is shown to include a standard horizontal sync pulse H and color burst C that occurs during the blanking level of the horizontal sync, followed by the closed caption signal. The closed caption signal co ists of seven cycles of the 0.503 MHz frequency, followed by three logic bits--two 0's and 1 start bit. The start bit is followed by two bytes of data which can be either control information or encoded characters.
The invention includes a search routine for finding line 21. This is accomplished by counting 17 horizontal pulses after the vertical sync pulse and opening a window to determine whether the run-in signal is present. In different environments, the initial count or line number may be other than 17. The window is opened a roximately 8 microseconds after the commencement of the horizontal sync pulse and remai open for a roximately 12 microseconds. The open period of the window corre onds to the occurrence of the seven cycle run-in signal. If the run-in signal is present during this period, the slice level of the run-in signal is optimized, i.e. set to produce a 50% duty cycle. The run-in signal and the su equent data or control information have the same DC level and format, and therefore it is advantageous to use the run-in signal to adjust the slice level to produce the proper slice level for the su equent data.
With reference to FIGS. 3A-3E, the operation of the automatic slice level adjustment circuit will be described. It should be noted initially that the prescribed frequency of the run-in signal is known as well as the frequency of the dot clock that is used in the receiver, which in the preferred embodiment, is a roximately 8 MHz. Accordingly, the number of "dot clocks" that should occur during one period of the run-in signal is known, and a simple counter and comparator may be used to verify the frequency and the number of cycles of the run-in signal. The dot clock sampling signal is schematically illustrated in FIG. 3A and one cycle of the run-in signal is illustrated in FIG. 3B, with the period T illustrated as one cycle of the run-in signal. In the depiction, there are 16 dot clocks per period T. Thus it is a relatively simple routine to calculate the number of dot clocks that should a ear during a cycle of the run-in signal. This figure is programmed into a register and compared with the number of samples detected (by the clock) between su equent zero cro ings of the run-in signal to determine whether the detected signal is of proper frequency. If it is, it is a umed to be the run-in signal and the dot clock is synchronized thereto. A uming that the run-in signal is present, the ratio of positive samples to negative samples detected may be readily determined to adjust the slice level to produce a pulse width modulated signal with a 50% duty cycle. In FIG. 3B, there is a high level and a low level shown on the run-in signal, with high indicating a high slice level and low indicating a low slice level. FIG. 3C illustrates this graphically and shows the samples detected when the slice level is too high. Clearly, more negative-going samples are produced than positive-going samples. The D/A converter 20 produces voltages corre onding to the samples, which voltages, when filtered, produce a DC potential that reflects the ratio of positive and negative samples over the period T for the i ut of data slicer 12. In FIG. 3D, the number of positive samples is equal to the number of negative samples during the period T of the run-in signal, which is the desirable 50% duty cycle condition. In FIG. 3E, the results of slicing at too low a level are illustrated and the number of positive samples, produced during the period T, is greater than the number of negative samples, resulting in a potential that is above the desired DC potential for a 50% duty cycle. Thus the D/A converter 20, in conjunction with filter 16, functio as a pulse width modulator that produces a direct current voltage for the i ut of data slicer 12 that reflects the duty cycle of the sliced run-in signal. As mentioned, the slice level of the run-in signal is used to correctly set the slice level of the following data. In the automatic mode, the duty cycle is automatically adjusted to be 50%. In the manual or override mode, an arbitrary number is a lied to the D/A converter 20, which when filtered, produces a DC level at the i ut of slicer 12 that develo a corre onding slice level. The arbitrary number is determined as desired by the viewer or by the software. This override arrangement permits manual software control of the data slice level should that be nece ary or desirable.
Reverting to FIG. 2, a series of three bits, co isting of two 0 bits and a 1 bit (start bit), follow the run-in signal. The start bit identifies the time at which the sampling counter clock is initiated for sampling the su equent bytes of data. The system is adaptable and the sampling rate determined for the sampling counter is determined by the run-in signal. To illustrate, should the system determine that 8 dot clocks occur between zero cro ings of the run-in signal, that number will be used to develop the sampling points for the su equent two bytes of data. Thus the data will be sampled every 8 dot clocks. It will be a reciated that should greater accuracy be desired, the pattern of dot clocks developed during the seven cycles of run-in signal may be "remembered" and repeated to sample the su equent data. If the number of dot clocks occurring between succe ive zero cro ings of the run-in signal is 8-8-9-8, for example, that 8-8-9-8 pattern can be repeated to sample the su equent two bytes of data. Such patter will occur because the dot clock frequency and the run-in signal frequency are not synchronized and develop a beat frequency. Using the same pattern found in the run-in signal improves sampling accuracy. In the preferred embodiment, only one cycle of run-in signal is used to determine the su equent sampling pattern for the line. The data sampling method is claimed in copending a lication Ser. No. 07/781,059, above.
As discu ed above, with most television receivers, simply counting horizontal sync pulses after the vertical sync pulse will not reliably find line 21 (or any particular line in the VBI). The disclosed search system will automatically find line 21. The particular algorithm used, however, is representative and should not be co idered limiting. After the vertical blanking interval, an arbitrary count of 17 horizontal sync pulses is used to trigger the development of the window illustrated in FIG. 2A. After the 17th horizontal pulse, a 10.74 microsecond delay is incorporated, followed by a dot clock controlled counter that begi sampling the video i ut. If line 21 (in the first field) is present and includes captioned data, the run-in signal will a ear. The dot clock controlled sampling will develop a series of positive and negative samples corre onding to the positive and negative portio of the sinewave run-in signal. The number of samples (or dot clocks) occurring between zero cro ings of the signal is determined for a uring that the frequency of the signal is correct, as mentioned above, and the number of positive and negative samples during a period T is used to determine the duty cycle. Should no clock run-in signal be detected, the algorithm changes the initial horizontal pulse count number, which cause the window to be opened at a different horizontal line in the VBI. In the algorithm of the preferred embodiment, the count is changed from 17 to 18 and another search is conducted with a window again being opened to check for the run-in signal. If no run-in signal is found, the counter is incremented by one and a search conducted until 20 horizontal pulses are counted before the window is opened. If the run-in signal is still not found, it is a umed that the field is wrong and a change is made to search similar lines in the o osite field, begi ing with line 15 and counting through line 20. This is accomplished with a first counter that introduces a 20 microsecond delay after the vertical sync and a second counter that ope a 16 microsecond wide window to determine whether a horizontal pulse is present in the video signal. The different fields are determined as follows. If a low is found during the 16 microsecond window, it is a umed that the field is odd. If no low is found and a horizontal pulse is found, it is the even field. A flag is set in a register to indicate the odd field and this flag is periodically checked by the software to verify that the correct field is being acce ed. Once the line with captioned data is found, the software remembers the initial horizontal pulse count number and the correct field and immediately counts to the proper line after the vertical sync. Should the run-in signal be mi ing due to a drop out, a change in cha el, or the like, the search algorithm is reinitiated to find line 21 with the captioned data. It may be seen that with the system, the captioned data may be placed on other than line 21 of the odd field and still be automatically and reliably found, although the standards dictate line 21, which simplifies things.
FIG. 4 is a flow chart indicating the operation of the system of the invention begi ing with the selection of a field (odd or even) setting of N and detection of the vertical sync. Counting of the initial number N of horizontal pulses after the vertical sync to reach a "target" line (hopefully line 21) is carried out. Thereafter the number of dot clock samples detected over the period of the sampled signal determines whether the sampled signal is the run-in signal, i.e. whether the sampled signal has the correct frequency. If the run-in signal is not found, a search routine is commenced during which different lines in the vertical blanking interval are addre ed and tested for the presence of the run-in signal. If none of the searched lines yield the run-in signal, a shift is made to the o osite field and the routine is run again. This routine is continually run as long as the captioned data decode mode is selected by the user. When the line with the run-in signal is found, and the system is operating in an automatic mode, the duty cycle of the sliced run-in signal is automatically established at 50%. Should the manual mode be selected, an override of the automatic mode is in effect and the duty cycle is determined by the particular number that is loaded into the D/A converter by the software. Finally, when the a ropriate duty cycle of the sampled run-in signal is produced, the start bit is found, and in conjunction with the sample rate established by the number of dot clocks that occurred between succe ive zero cro ings of the run-in signal, coordinates the sampling of the su equent data in the line.
Thus the system of this invention enables the slice level of the data to be automatically adjusted to the optimum 50% duty cycle level. Also, the captioned data may be reliably found without relying upon a precise indication of the initiation of the vertical blanking interval in the television receiver and the sampling pattern for the data to be accurately determined based upon the run-in signal frequency. This is all accomplished through simple logic and software and simple hardware such as counters and comparators. It is recognized that numerous changes and modificatio in the described embodiments of the invention will be a arent to those skilled in the art without departing from its true irit and scope. The invention is to be limited only as defined in the claims. | Copyright 2004-2011 FreePatentsOnline.com. All rights reserved.Data Slicing Techniques for UH
Data Slicing Techniques for UH
Amplitude-shift keying (ASK) and on-off keying (OOK) receivers are used for intermittent low-data-rate a licatio like RKE, home security, garage-door openers, and remote controls. The data that comes to an ASK or OOK receiver from a remote tra mitter is reco tructed in the data slicer. The data slicer is, therefore, an integral part of ASK and FSK receivers that operate in the 260MHz to 470MHz short-range UHF band under the rules of FCC Part 15.231. This a lication note explai the operation of the data slicers found in Maxim's UHF receivers, including the MAX1470, MAX1473, and MAX1471, and tra ceivers like the MAX7030 and MAX7032.
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Introduction
In its simplest form, the data slicer is an analog comparator that compares the demodulated ASK signal with a threshold. If the demodulated signal voltage exceeds the threshold, the comparator output goes high, usually to the su ly voltage. If the demodulated signal goes below the threshold, the comparator output goes low, usually zero volts or ground.
This a lication note reviews two a ects of data slicing: forming the comparator threshold, and preventing the comparator output from 'chattering' when no signal is present. The latter operation, often cal
'squelching', can be done by introducing simple voltage offsets onto either pin of the data comparator. This offset can come directly from the power su ly or from using hysteresis, which is the proce of feeding back part of the output voltage from the data slicer comparator.
We will show three different ways to form the threshold, and three different ways to introduce squelch, all of which can be done by adding a few external resistors and/or capacitors.
Demodulated ASK Signal
The Maxim ASK receivers use a demodulator that is a carefully designed limiting IF amplifier. This amplifier produces a voltage that is proportional to the logarithm of the i ut IF signal power. When no signal is present, the voltage formed by the amplifier co ists of a quiescent DC value with a small time-varying noise voltage riding on it.
Figure 1
shows the waveform for the demodulator output in re o e to an ASK-modulated signal. The waveform will go back and forth between the quiescent voltage, V
, when the signal is keyed off, and the signal voltage, V
, when the signal is keyed on. In the , V
is typically about 1.2V and V
ranges from about 40mV at se itivity to about 1V at very high signal levels.
Figure 1. ASK demodulator output.
Data Slicer Block Diagrams
Figure 2
shows a block diagram of the MAX1473 ASK receiver. This a lication note focuses on the three operational amplifiers and the seven pi at the bottom right of the diagram that comprise the data slicer. The same functional blocks are redrawn in
Figure 3
to illustrate the function of each circuit more clearly. The reference designators for the resistors and capacitors in these figures are the same as those in the
schematic. The operational amplifier, U1, and its components form the Sallen-Key data filter, which smoothes the output of the detected amplitude from the ASK demodulator. The operational amplifier, U2, and its components form the data slicer comparator, while the peak-detecting operational amplifier, U3, and its components form the peak-detector output. We can now focus on individual parts of this circuit to understand the various optio within the data-slicing operation.
Figure 2. Block diagram of the MAX1473 ASK receiver.
Figure 3. Block diagram of the data-slicer blocks in the MAX1473, including external components.
The Fundamental Data-Slicing Circuit
Figure 4
shows the simplest data-slicing circuit. The output of the data filter, DFO, goes to the positive pin of the data slicer comparator, DSP, and also forms the slicing threshold voltage at DSN by pa ing through a simple RC lowpa filter. When the detected and filtered ASK signal, DFO, pa es through the lowpa filter formed by R1 and C4 and settles, the DC value of the DSN pin is halfway between the maximum and minimum voltage of that signal.
Figure 5
illustrates the waveforms at DSP and DSN, using the voltages V
from Figure 1. Notice that the steady-state voltage at DSN is V
/2. This circuit functio well when the received data stream has enough extra bits at the begi ing of a packet or frame (in the form of a preamble or synch pattern) that it can afford to lose while the R1-C4 circuit charges up to the correct slicing threshold. When the first bits of a sequence need to be detected, the circuit that forms the threshold voltageat DSN needs to reach that voltage quickly. This is where the peak detector can help.
Figure 4. Fundamental data-slicing circuit.
Figure 5. DSN and DSP signal for fundamental data-slicing threshold formation.
Data Slicer with Rapid Threshold Formation
Adding a voltage from the peak detector in the ASK receivers can accelerate the formation of the data-slicing threshold DSN. The circuit in
Figure 6
illustrates how the contributio to DSN from the data filter and the peak detector combine to produce a rapidly re onding threshold voltage. By co idering DFO and PDOUT as two independent voltage sources, we can use the Superposition technique (find the re o e from each source alone, then add the re o es) to determine the voltage at DSN. The contribution from the peak detector is an i tantaneous voltage jump through the capacitive divider formed by C13 and C4. This voltage jump decays to a steady-state value determined by the resistive divider formed by R1 and R2. The contribution from the R1-C4 lowpa filter is the same slowly rising threshold from the fundamental data-slicer circuit. By choosing the two R and two C values carefully, the two contributio can complement one another and form a threshold voltage at DSN that ideally jum immediately to the correct threshold and stays there.
Figure 6. Circuit and waveforms for rapid threshold formation.
Figure 7
illustrates two DSN waveforms for two different sets of resistors and capacitors. The combination of components that produces a threshold voltage at DSN closest to an i tantaneous jump obeys the guideline below:
Figure 7. Combined DSN voltage vs. time using a peak detector.
We can illustrate the choice of the R's and C's with a ecific example. For an ASK data rate of 4k NRZ, the R1-C4 lowpa filter should have a time co tant of about 5-bit intervals, which is 5 x 0.25ms, or 1.25ms. A good choice of R1 and C4 is:
R1 = 25 k
and C4 = 0.047 F
We choose C13 equal to C4, and make R2 much larger than R1 (a factor of 10 is good):
R2 = 250 k
and C13 = 0.047 F
This choice will cause the threshold voltage DSN to jump from V
/2, then settle to V
+ 0.55V
Notice that this a roach to establishing a rapid slicing threshold creates a small error in the threshold. Moreover, the time co tant a ociated with the threshold voltage's change from its initial to final value, which is a very small change, is given by the product below:
Time Co tant = (R1 || R2 x (C4 + C13))
This is a roximately twice the time co tant of the R1-C4 smoothing circuit. We could correct for this change by reducing each capacitor value, but that is not nece ary. Because the threshold changes very little after its initial jump, the time co tant is not as critical as it is in a circuit that lacks the peak-detector contribution.
Data Slicer with Dual Peak Detectors
There is a minor drawback to using the single peak detector in combination with the R-C smoothing circuit to form the slicing threshold: the final threshold value differs slightly from its ideal value which is halfway between the maximum and minimum voltage that comes from the data filter.
Using a maximum and minimum peak detector is one way to improve the rapid establishment of the slicing threshold. The
ASK/FSK receiver, the
FSK receiver, and the // tra ceivers have maximum and minimum peak detectors so that the single R-C smoothing circuit is not needed.
Figure 8
shows these peak detectors, each with an external resistor and capacitor. Each capacitor holds the peak voltage, and each resistor provides a discharge path for the a ociated capacitor. This design allows the peak detectors to dynamically follow any peak changes in the data-filter output voltages. The maximum and minimum peak detectors can be used together to form a data-slicer threshold voltage at a value midway between the maximum and minimum voltage levels of the data stream. The RC time co tant of these R-C pairs should be set to about five times the bit interval, as it is in the simple threshold smoothing circuit described earlier in this a lication note.
Figure 8. Data-slicer circuit with maximum and minimum peak detectors.
If something causes a significant change in the magnitude of the baseband signal, such as an AGC gain switch or a power-up tra ient, the peak detectors may 'catch' a false level. If a false peak is detected, the slicing level is incorrect. Because the RC time co tants are several bits long, the peak detectors may not recover rapidly. The Maxim receivers with dual peak detectors, however, all have at least one provision for resetting the peak detector outputs: the receivers momentarily allow the peak detectors to track the signal. In the MAX7042 FSK receiver, the peak detectors are reset by momentarily pulling the ENABLE pin low, then returning it to a logical high setting. The MAX7030 and MAX7031 tra ceivers reset the peak detectors the same way, but also reset the peak detectors whenever the AGC function changes state or the T/R switch enters the receive state. The MAX1471 ASK/FSK receiver and the MAX7032 ASK/FSK tra ceiver reset the peak detectors through their serial ports, and also automatically reset the peak detectors whenever the receiver emerges from the sleep mode.
Adding Basic Squelch to the Data Slicer
In the a ence of an ASK signal, the ASK detector output co ists of a DC voltage with a time-varying noise voltage whose peak-to-peak value is about 20mV. This noise voltage a ears as the data-slicer comparator swings back and forth acro the DSN threshold voltage, causing the comparator's output to 'chatter', that is, to jump rapidly and randomly back and forth between the su ly voltage and ground. This behavior often wakes up microproce ors u ece arily and can sometimes add noise to the power-su ly lines. One way to stop this chatter is to use a simple squelch circuit, which adds a small DC offset to either the positive (DSP) or negative (DSN) pin of the data slicer.
Figure 9
shows simple squelch circuits that use the power su ly as the source of the DC offset. Usually, all you need is a large resistor that is 50 to 100 times the value of the resistor between the data-filter output DFO and either i ut pin on the comparator. In the first circuit of Figure 9, the small offset is added to DSP. If the offset is about 30mV, then two things will ha en. Firstly, the noise riding on the DC voltage at DSP in the a ence of a signal will never take the DSP voltage below the level of the threshold at DSN; and, secondly, the DATAOUT pin will be held high, i.e., V
. In the second circuit of Figure 9, the offset is added to DSN. Now the noise that rides on the DC voltage at DSP will never take the DSP voltage above the increased threshold at DSN and the DATAOUT pin will be held low, i.e., GND. The squelch circuit reduces se itivity slightly (about 1dB to 2dB when the resistive divider is chosen carefully), and causes a slightly wider positive data pulse and slightly narrower negative data pulse at DATAOUT when a demodulated signal is present.
Figure 9. Two simple squelch circuits using a su ly voltage.
Squelch from Dual Peak Detectors
Another simple squelch circuit can be formed by using the dual peak detectors in Figure 8 above. Making the two resistors slightly unequal will shift the threshold above or below the midpoint of the two peak voltages, depending on which resistor is larger. If the threshold is set slightly above the midpoint by 30mV to 50mV, the DATAOUT pin will stay low when no signal is present. Similarly, if the threshold is set slightly below the midpoint, the DATAOUT pin will stay high when no signal is present.
Adding Resistive Hysteresis to the Data Slicer
You can also use a large resistor to tie the DATAOUT pin from the data slicer to the DSP pin .
Figure 10
shows the equivalent circuit for resistive hysteresis. This a roach has almost the same effect as co ecting V
to the DSP pin through a resistor. The only difference here is that, when a demodulated signal is present, the small offset at DSP is there only during the positive swing of the demodulated data. Hence, the increase in the width of the positive data pulse at DATAOUT is slightly le , because the leading edge of the positive data pulse is not advanced by the presence of an offset.
Figure 10. Resistive hysteresis circuit for squelch function.
Adding Capacitive Hysteresis to the Data Slicer
Capacitive hysteresis offers a compromise between exce ive chattering of the DATAOUT signal and the reduced se itivity that comes from a squelch or resistive hysteresis. The circuit for capacitive hysteresis is shown in
Figure 11
Just as in resistive hysteresis, a small fraction of the DATAOUT signal is fed back to the DSP pin, this time through the capacitive divider C7-C9. Typical capacitor values are 10pf for C7 and 1000pf for C9. The offset added to DSP differs because it is a tra ient offset that decays with a time co tant given by:
R8 x (C9 + C7)
Depending on the length of the time co tant, the offset kee the noise on DSP from going below the slicing threshold until the offset decays. This effectively increases the time that the DATAOUT pin stays high, thereby reducing the frequency of the DATAOUT chatter. While capacitive hysteresis does not eliminate chatter altogether, it reduces the number of tra itio .
Notice that the presence of C9 creates another lowpa filter with R8 in the demodulated ASK signal path. The pole a ociated with this filter time co tant should be larger than the bandwidth of the Sallen-Key data filter, so that it does not make the filtered signal too sluggish.
Figure 11. Capacitive hysteresis circuit and waveforms.
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